AD4084BBCZ datasheet(9/94 Pages) AD

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Data Sheet

AD4084

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 9 of 94

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

A1, A2, A3

VDD11

1.1V ADC Core Supplies. These supply pins are internally decoupled by four 470nF

capacitors to GND.

When power is supplied to VDDLDO (B3), an internal LDO voltage regulator produces

the 1.1V required at these pins. The voltage regulator is automatically powered on

when VDDLDO is greater than 1.4V.

If VDDLDO is left disconnected, the required 1.1V must be supplied to these pins from

an external source.

A4, A5

CNV+, CNV−

Convert Start Inputs. This pin pair serves as the conversion control input. A conversion

is initiated on the rising edge of the convert signal.

These inputs are, by default, configured in complementary metal-oxide semiconductor

(CMOS) mode, in which CNV− must be tied to IOGND, and the convert signal is

applied to CNV+. In the LVDS data interface mode, the convert start input can be

optionally configured in LVDS mode, in which case, the convert signal is applied

differentially to CNV+ and CNV− and an external 100Ω termination resistor must be

placed across these pins. See the ADC Conversion Control section for further details.

IOVDD

1.1V Digital Interface Supply Rail. This supply is internally decoupled by a 220nF

capacitor to IOGND.

When power is supplied to VDDLDO (B3), an internal LDO voltage regulator produces

the 1.1V required at this pin. The voltage regulator is automatically powered on when

VDDLDO is greater than 1.5V.

If VDDLDO is left disconnected, the required 1.1V must be supplied to this pin from an

external source (typically the host controller interface supply).

CLK−/DCS

Data Interface Clock Input (CLK−)/Data Interface Chip Select (DCS) Multifunction Pin.

In LVDS data interface mode (default), this pin serves as half of the differential data

clock input, and an external 100Ω termination resistor must be present between it and

the CLK+ pin.

In SPI data interface mode, this pin functions as a chip select input (data interface chip

select).

B1, B2, C1, C2, F5,

F6, G5

REFGND

Reference Grounds. Connect any external reference decoupling capacitors across

REFIN and REFGND. REFGND must be tied with a low impedance path to GND.

VDDLDO

LDO Supply Rail Input.

This supply rail is internally decoupled by a 220nF capacitor to GND. The two internal

1.1V LDO voltage regulators can be supplied from a source connected to this input

in the 1.5V to 2.7V range. If this pin is left open, the internal regulators automatically

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