AD4084BBCZ datasheet(19/94 Pages) AD

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Data Sheet

AD4084

THEORY OF OPERATION

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Rev. 0 | 19 of 94

TRANSFER FUNCTION

The AD4084 digitizes the full-scale difference voltage of 2 × VREFIN

into 216 levels, resulting in an LSB size of 91.55μV with VREFIN =

3.0V. Note that 1 LSB at 16 bits is approximately 15.26ppm.

Table 7 summarizes the mapping of input voltages to differential

output codes.

Figure 34. ADC Ideal Transfer Function for the Differential Output Codes

(FSR Is Full-Scale Range)

Table 7. Input Voltage to Output Code Mapping

Description

Analog Input Voltage

Difference (IN+ − IN−,

Volts)

Digital Output Code (Twos

Complement, Hex)

FS − 1 LSB

+VREFIN × (1 − 1/215)

0x7FFF

Midscale + 1 LSB +VREFIN/215

0x0001

Midscale

0x0000

Midscale − 1 LSB −VREFIN/215

0xFFFF

−FS + 1 LSB

−VREFIN × (1 − 1/215)

0x8001

−FS

−VREFIN

0x8000

EASY DRIVE ANALOG INPUTS

The AD4084 signal input consists of a fully differential input pair

(IN+ and IN−), each connected to the input sampling network

(series resistance (RS) and sampling capacitance (CS)) and a pair

of auxiliary inputs (AUXIN+ and AUXIN−) that provide a reference

to the sampling network linearization circuits. An equivalent circuit

model of the analog input is presented in Figure 35.

Figure 35. Equivalent Analog Input Circuit Model

In this model, the input sampling network was simplified to consist

of two ideal switches, RS and CS, for the ADC in acquisition mode.

The typical value for CS is 23.5pF and RS is 26Ω.

The parasitic capacitance related to the pin connection (CPIN) is

modeled as a shunt capacitor between the pin and device ground

terminal (GND). The capacitance includes parasitic capacitance

formed from the physical interface, routing in the package substrate

and the device input protection circuits. The CPIN value is typically

4.5pF. The input protection circuit for the AD4084 is modeled as

diode clamps to the GND and VDD33 supply rails.

The external low-pass filters (LPFs) constructed from RFILTIN and

CFILTIN and RFILTAUX and CFILTAUX are band-limiting filters for the

primary and auxiliary paths, respectively.

The combination of RFILTIN and CFILTIN is often referred to as

anti-aliasing filters because these filters do introduce a single-pole

filter in the analog input signal path. However, the function of CFILTIN

is more complex and must be carefully considered. Conversion

through a SAR involves sampling the voltage from an internal ca-

pacitor, represented by CS in the Figure 35, which typically occurs

in two phases in time, ϕ1 and ϕ2 . During the first phase, the ϕ1

switches are closed, the ϕ2 switches are opened, and the sampling

capacitors (CS) are charged to the analog input voltages present at

IN+ and IN−. During the second phase, the ϕ1 switches are opened,

the ϕ2 are closed, and the ADC converts the voltage onto CS.

An additional short time phase exists where the CS charge is

reset after the conversion is complete. This process repeats for

each new ADC conversion. The transfer of charge from the ADC

analog input pins to CS, due to the closing of the switches in

each conversion cycle, creates a demand at the analog input pin.

It is important to ensure that the voltage presented at the input

pin is undisturbed by the internal ADC activity so that the voltage

can be converted with the highest accuracy. Each new conversion

presents a disturbance, or kick, at the input. The faster the ADC

conversion rate is, the more frequent the occurrence of these kicks.

An ADC driver is used to ensure that the input voltage, disturbed

by the kick at each sampling instance, is fully settled to the required

ADC resolution prior to the next sample being acquired. The ADC

driver amplifier must have a wide enough output bandwidth to settle

the voltage in time for each sample, which creates a signal chain

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