7.5 Layout

7.5.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including

the following guidelines:

• Noise can propagate into analog circuitry through the power pins of the op amp and the circuit as a

whole. Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground. Place

the capacitors as close to the device as possible. A single bypass capacitor from V+ to ground is sufficient for

single supply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective

methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to ground

planes. A ground plane helps distribute heat and reduces EMI noise pickup. Physically separate digital and

analog grounds paying attention to the flow of the ground current.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed

to in parallel with the noisy trace.

• Place the external components as close to the device as possible.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

• Clean the PCB following board assembly for best performance.

• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic

package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture

introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake

at 85°C for 30 minutes is sufficient for most circumstances.

7.5.1.1 Thermal Considerations

Through normal operation, the op amps can self-heat. Self-heating is a natural increase in the die junction

temperature that occurs in every amplifier. This self-heating is a result of several factors, including quiescent

power consumption, package thermal resistance, PCB layout, and device operating conditions.

Operate the OPAx596 within the rated junction temperature, TJ, range to avoid thermal shutdown. Use the

Equation 3 to determine the estimated TJ

TJ=PD × RθJA+TA

(3)

In a quiescent state, PD is given by the product of the power supply and the quiescent current of the op

amp. Equation 4 shows the calculation of TJ for the OPAx596 assuming an 85V power supply is used and an

operating temperature of 25°C.

TJ= 85V ×490μA ×165.4°CW+25°C

(4)

TJ=31.89°C

(5)

The low power consumption of the OPAx596 causes minimal self-heating even in a small SOT23-5 package as

given by Equation 5. In a loaded condition, PD is equal to addition of the quiescent power, PDQ and the power

dissipated by the output stage, PDL. The worst-case condition is given when the output voltage is equal to ½

of either supply rail (assuming symmetrical supplies, V+ and V-). In a worst-case condition, PDL is given by

Equation 6.

PDL= V+ 24×RL

(6)

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OPA596, OPA2596

SBOSA42B – JUNE 2024 – REVISED DECEMBER 2025

Copyright © 2025 Texas Instruments Incorporated

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