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VL6624 Datasheet(PDF) 10 Page - STMicroelectronics

Part # VL6624
Description  1.3 Megapixel single-chip camera module
PDF  106 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

VL6624 Datasheet(HTML) 10 Page - STMicroelectronics

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System architecture
VL6624/VS6624
10/106
3
System architecture
The VS6624 consists of the following main blocks:
●
SXGA-sized pixel array
●
Video timing generator
●
Video pipe
●
Statistics gathering unit
●
Clock generator
●
Microprocessor
A simplified block diagram is shown
Figure 1.
Figure 1.
VL6624/VS6624 simplified block diagram
3.1
Operation
A video timing generator controls a SXGA-sized pixel array to produce raw bayer images.
The analogue pixel information is digitized and passed into the video pipe. The video pipe
contains a number of different functions (explained in detail later). At the end of the video
pipe data is output to the host system over an 8-bit parallel interface along with qualification
signals.
The whole system is controlled by an embedded microprocessor that is running firmware
stored in an internal ROM. The external host communicates with this microprocessor over
an I²C interface. The microprocessor does not handle the video data itself but is able to
control all the functions within the video pipe. Real-time information about the video data is
gathered by a statistics engine and is available to the microprocessor. The processor uses
Microprocessor
SDA
SCL
CE
AVDD
HSYNC
PCLK
D[0:7]
CLK
VSYNC
Clock
Generator
I²C
Statistics
Gathering
Video Timing
Generator
RESET
VREG
VDD
I²C Interface
FSO
GND
GND
SXGA
Pixel
Array
Video Pipe



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