LXT362 datasheet(39/48 Pages) INTEL

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Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT362

Datasheet

Table 23. Digital Characteristics

Parameter

Sym

Min

Typ

Max

Unit

Test Conditions

High level input voltage 1,2 (pins 1-4, 17, 23-25)4

VIH

2.0

––

Low level input voltage 1,2 (pins 1-4, 17, 23-25)4

VIL

––

0.8

High level output voltage 1,2 (pins 6-8, 10, 12, 23, 25)4

VOH

2.4

––

VIOUT = 400

µA

Low level output voltage 1,2 (pins 6-8, 10, 12, 23, 25)4

VOL

––

0.4

IOUT = 1.6 mA

High level input voltage 3 (pins 5, 9, 11, 26-28)4

VIH

3.5

––

Midrange input voltage 3 (pins 5, 9, 11, 26-28)4

VIM

2.3

–

2.7

Low level input voltage 3 (pins 5, 9, 11, 26-28)4

Host mode

Hardware

mode

VIL

–

0.8

1.5

Input leakage current

ILL

–

±50

µA

Three-state leakage current 1 (all outputs)

–

±10

µA

TTIP/TRING leakage current (pins 13, 16)4

ITR

––

±1.2

in Idle and

Power Down

1. Functionality of pins 23 and 25 depend on mode. See Host mode and Hardware mode description.

2. Output drivers will output CMOS logic levels into CMOS loads.

3. As an alternative to supplying 2.3 - 2.7 V (Midrange logic level) to these pins, they may be left open.

4. Referenced pin numbers are for the PLCC package. Refer to Figure 2 on page 8 for the corresponding QFP pins.

Table 24. Analog Characteristics

Parameter

Min

Typ1

Max

Unit

Test Conditions

Recommended output load on TTIP/TRING

–

200

Ω

AMI Output Pulse Amplitudes

DSX-1, DS1

2.4

3.0

3.6

RL = 100

Ω

Jitter added by the transmitter2

10 Hz - 8 kHz 3

––

0.02

8 kHz - 40 kHz 3

––

0.025

10 Hz - 40 kHz3

––

0.025

Broad Band

––

0.05

Receiver sensitivity

@ 772 kHz

Mode 1 (EC1 = 1)

(Long-Haul)

–

See Table 10 for Gain

Setting

Mode 2 (EC1 = 0)

(Long-Haul)

–

Mode 3 (EC4 = 1)

(Short-Haul)

–

13.6

Allowable consecutive zeros before LOS

160

175

190

–

Input jitter tolerance

10 kHz - 100 kHz

0.4

––

0 dB line

AT&T Pub 62411

1 Hz 3

138

––

Jitter attenuation curve corner frequency 4

–

selectable in data port

1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

2. Input signal to TCLK is jitter-free. The Jitter Attenuator is in the receive path or disabled.

3. Guaranteed by characterization; not subject to production testing.

4. Circuit attenuates jitter at 20 dB/decade above the corner frequency.

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