MSC8103SLASHD datasheet(50/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

2-10

Freescale Semiconductor

Physical and Electrical Specifications

2.6.4.1 Reset Operation

The reset control logic determines the cause of a reset, synchronizes it if necessary, and resets the appropriate logic

modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized

only on hard reset. Soft reset initializes the internal logic while maintaining the system configuration. The

MSC8103 has three mechanisms for reset configuration: host reset configuration, hardware reset configuration, and

reduced reset configuration.

2.6.4.2 Power-On Reset Flow

Asserting the PORESET external pin initiates the power-on reset flow. PORESET should be asserted externally for at

least 16 input clock cycles after external power to the MSC8103 reaches at least 2/3 VCC. As Table 2-13 shows, the

MSC8103 has five configuration pins, four of which are multiplexed with the SC140 EONCE Event (EE[0–1],

EE[4–5]

) pins and the fifth of which is the RSTCONF pin. These pins are sampled at the rising edge of PORESET. In

addition to these configuration pins, three (MODCK[1–3]) pins are sampled by the MSC8103. The signals on these

pins and the MODCK_H value in the Hard Reset Configuration Word determine the PLL locking mode, by

defining the ratio between the DSP clock, the bus clocks, and the CPM clock frequencies.

Table 2-13.

External Configuration Signals

Description

Settings

RSTCONF

Reset Configuration

Input line sampled by the MSC8103 at the rising edge of

PORESET.

Reset Configuration Master.

Reset Configuration Slave.

DBREQ/ EE0

EONCE Event Bit 0

Input line sampled after SC140 core PLL locks. Holding EE0

high when PORESET is deasserted puts the SC140 into

Debug mode.

SC140 starts the normal processing

mode after reset.

SC140 enters Debug mode immediately

after reset.

HPE/EE1

Host Port Enable

Input line sampled at the rising edge of PORESET. If

asserted, the Host port is enabled, the system data bus is

32-bit wide, and the Host

must program the reset

configuration word.

Host port disabled (hardware reset

configuration enabled).

Host port enabled.

BTM[0–1]/

EE[4–5]

Boot Mode

Input lines sampled at the rising edge of PORESET, which

determine the MSC8103 Boot mode.

MSC8103 boots from external memory.

MSC8103 boots from HDI16.

Reserved.

Table 2-14.

Reset Timing

No.

Characteristics

Expression

Min

Max

Unit

Required external PORESET duration minimum

•

CLKIN = 18 MHz

•

CLKIN = 75 MHz

/ CLKIN

888.8

213.3

—

Delay from deassertion of external PORESET to deassertion of

internal PORESET

•

CLKIN = 18 MHz

•

CLKIN = 75 MHz

1024

/ CLKIN

56.89

13.65

µs

Delay from deassertion of internal PORESET to SPLL lock

•

SPLLMFCLK = 18 MHz

•

SPLLMFCLK = 25 MHz

800

/ SPLLMFCLK

44.4

32.0

µs

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