MSC8103SLASHD datasheet(51/104 Pages) FREESCALE

51 / 104 page

AC Timings

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

2-11

2.6.4.3 Host Reset Configuration

Host reset configuration allows the host to program the reset configuration word via the Host port after PORESET is

deasserted, as described in the MSC8103 Reference Manual. The MSC8103 samples the signals described in Table

2-13 one the rising edge of PORESET when the signal is deasserted.

If HPE is sampled high, the host port is enabled. In this mode the RSTCONF pin must be pulled up. The device

extends the internal PORESET until the host programs the reset configuration word register. The host must write

four 8-bit half-words to the Host Reset Configuration Register address to program the reset configuration word,

which is 32 bits wide. For more information, see the MSC8103 Reference Manual. The reset configuration word is

programmed before the internal PLL and DLL in the MSC8103 are locked. The host must program it after the

rising edge of the PORESET input. In this mode, the host must have its own clock that does not depend on the

MSC8103 clock. After the PLL and DLL are locked, HRESET remains asserted for another 512 bus clocks and is

then released. The SRESET is released three bus clocks later (see Figure 2-7).

Delay from SPLL lock to DLL lock

•

DLL enabled

— BCLK = 18 MHz

— BCLK = 75 MHz

•

DLL disabled

3073

/ BLCK

—

170.72

40.97

0.0

µs

Delay from SPLL lock to HRESET deassertion

•

DLL enabled

— BCLK = 18 MHz

— BCLK = 75 MHz

•

DLL disabled

— BCLK = 18 MHz

— BCLK = 75 MHz

3585

/ BLCK

512

/ BLCK

199.17

47.5

28.4

6.83

µs

Delay from SPLL lock to SRESET deassertion

•

DLL enabled

— BCLK = 18 MHz

— BCLK = 75 MHz

•

DLL disabled

— BCLK = 18 MHz

— BCLK = 75 MHz

3588

/ BLCK

515

/ BLCK

199.33

47.84

28.61

6.87

µs

Note:

Value given for lowest possible CLKIN frequency 18 MHz to ensure proper initialization of reset sequence.

Table 2-14.

Reset Timing (Continued)

No.

Characteristics

Expression

Min

Max

Unit

MSC8103/D Datasheet(PDF) 51 Page - Freescale Semiconductor, Inc

MSC8103/D Datasheet(HTML) 51 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL