ST10R272L datasheet(59/77 Pages) STMICROELECTRONICS

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ST10R272L - ELECTRICAL CHARACTERISTICS

16.3.4

Demultiplexed Bus

VDD = 3.3 V ± 0.3 V

VSS = 0 V

TA = -40 to +85 °C

CL = 50 pF

ALE cycle time = 4 TCL + 2

tA + tC + tF (40 ns at 50 MHz CPU clock without waitstates)

Parameter

Symbol

Max CPU Clock 50MHz

Variable CPU Clock

1/2TCL = 1 to 50 MHz

min.

max.

min.

max.

ALE high time

7 +

–

TCL - 3 +

–ns

Address (P1, P4), BHE

setup to ALE

3 +

–

TCL - 7 +

–ns

Address setup to RD, WR

(with RW-delay)

t80

13 +

2tA

–

2TCL - 7 +

2tA –ns

Address setup to RD, WR

(no RW-delay)

t81

3 +

2tA

–

TCL - 7 +

2tA –ns

RD, WR low time

(with RW-delay)

t12

13 +

–

2TCL - 7 +

tC –ns

RD, WR low time

(no RW-delay)

t13

23 +

–

3TCL - 7 +

tC –ns

RD to valid data in

(with RW-delay)

t14

–

5 +

–

2TCL - 15

RD to valid data in

(no RW-delay)

t15

–

15 +

–

3TCL - 15

ALE low to valid data in

t16

–

15 +

tA + tC –

3TCL - 15

tA + tC

Address to valid data in

t17

–

20 + 2

tA +

–

4TCL - 20

+ 2

tA + tC

Data hold after RD

rising edge

t18

–

Data float after RD rising

edge (with RW-delay)1) 2)

t20

–

tF + 2tA

–2TCL - 5

tF + 2tA

Data float after RD rising

edge (no RW-delay)1 2

t21

–

5 +

tF +

–TCL - 5

tF + 2tA

Data valid to WR

t22

13 +

–

2TCL - 7 +

tC –ns

Table 18 Demultiplexed bus

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