ST10R272L datasheet(60/77 Pages) STMICROELECTRONICS

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ST10R272L - ELECTRICAL CHARACTERISTICS

Data hold after WR

t24

5 +

–

TCL - 5 +

–ns

ALE rising edge after RD,

t26

-5 +

–

-5 +

–ns

Address hold after RD, WR

t28

0 (no tF)

-9+

tF (tF>0)

–

0 (no

tF)

-9 +

tF (tF>0)

–ns

Address hold after WRH

t28h CC

-1 (no tF)

-8 +tF (tF>0)

–

-1 (no

tF)

-8 +

tF (tF>0)

–ns

Latched CS setup to ALE

t38

-7 +

3 +

-7 +

3 +

Unlatched CS setup to ALE t38u CC

3 +

–

TCL - 7 +

–ns

Latched CS low to Valid

Data In

t39

–

tC + 2tA

–

3TCL - 17

tC + 2tA

Unlatched CS low to Valid

Data In

t39u SR

–

tC + 2tA

–

4TCL - 17

tC + 2tA

Latched CS hold after RD,

t41

3 +

–

TCL - 7 +

–ns

Unlatched CS hold after RD,

t41u CC

0 (no tF)

-7 +tF (tF>0)

–

0 (no

tF)

-7 +

tF (tF>0)

–ns

Address setup to RdCs,

WrCs (with RW-delay)

t82

13 +

2tA

–

2TCL - 7 +

2tA –ns

Address setup to RdCs,

WrCs (no RW-delay)

t83

3 +

2tA

–

TCL - 7 +

2tA –ns

RdCS to Valid Data In

(with RW-delay)

t46

–

3 +

–

2TCL - 17 +

tC ns

RdCS to Valid Data In

(no RW-delay)

t47

–

13 +

–

3TCL - 17 +

tC ns

RdCS, WrCS Low Time

(with RW-delay)

t48

11 +

–

2TCL - 9 +

tC –ns

RdCS, WrCS Low Time

(no RW-delay)

t49

21 +

–

3TCL - 9 +

tC –ns

Data valid to WrCS

t50

13 +

–

2TCL - 7 +

tC –ns

Parameter

Symbol

Max CPU Clock 50MHz

Variable CPU Clock

1/2TCL = 1 to 50 MHz

min.

max.

min.

max.

Table 18 Demultiplexed bus

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