Advance Information

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com.

1

RMS132UAW

512K x 32Bits x 2Banks Low Power Synchronous DRAM

Description

These RMS132UAW are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits. These

products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are

synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input

and output voltage levels are compatible with LVCMOS.

Table1: Ordering Information

JEDEC standard 1.8V power supply.

• Auto refresh and self refresh.

• All pins are compatible with LVCMOS interface.

• 4K refresh cycle / 64ms.

• Programmable Burst Length and Burst Type.

- 1, 2, 4, 8 or Full Page for Sequential Burst.

- 4 or 8 for Interleave Burst.

• Programmable CAS Latency : 2,3 clocks.

• Programmable Driver Strength Control

- Full Strength or 1/2, 1/4 of Full Strength

• Deep Power Down Mode.

• All inputs and outputs referenced to the positive edge of the

system clock.

• Data mask function by DQM.

• Internal dual banks operation.

• Burst Read Single Write operation.

• Special Function Support.

- PASR(Partial Array Self Refresh)

- Auto TCSR(Temperature Compensated Self Refresh)

• Automatic precharge, includes CONCURRENT Auto Precharge

Mode and controlled Precharge.

Features

-25°C to 85°C

Temperature

Wafer

LVCMOS

1.8V/1.8V

133 MHz

RMS132UAW-75E

Package

Interface

VDD/VDDQ

Clock Freq.

Part No.

Emerging Memory & Logic Solutions Inc.

4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717

Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com