STLC5465B datasheet(67/101 Pages) STMICROELECTRONICS

67 / 101 page

VII - MICROPROCESSOR TIMING (continued)

1/f

TRO

TRI

MASTER CLOCK

(applie d to XTAL1 Pin)

Figure 56 : Token Ring

VII.8 - Token Ring Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

f : Masterclock frequency

32.768

MHz

Delay between Masterclock Rising Edge and Edges of TRO Pulse

delivered by the MHDLC (10pF)

VDD =5V

V DD = 3.3V

Set-up Time TRI/Masterclock Masterclock Falling Edge

Hold Time TRI/Masterclock Falling Edge

VII.9 - Master Clock Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

Masterclock Frequency

32.768

MHz

1/f

Masterclock Period

30.3

30.5

33.3

Masterclock High

Masterclock Low

1/f

MASTER CLOCK

(applied to XTAL1 Pin)

Figure 57 : Master Clock

Crystal parameters:

a) frequency

f (typically 32768.00 kHz)

b) Mode

fundamental

c) Resonance

parallel

d) Load Capacity

Cl= 30pF

in accordance with 2 capacitors (47 pF each of

them) the first capacitor is soldered nearest pin 2

(XTAL1) and nearest the ground, the second ca-

pacitor is soldered nearest pin 3 (XTAL2) and

nearest the ground.

e) Serial resistor

40 Ohms max

To reduce the drive level, the Crystal parameters

can be:

a) frequency

f (typically 32768.00 kHz)

b) Mode

fundamental

c) Resonance

parallel

d) Load Capacity

Cl = 20pF

in accordance with 2 capacitors (33 pF each of

them)

e) Serial resistor

40 Ohms max

N.B It is not necessary to add an external bias

resistor between XTAL1 pin and XTAL2 pin. This

resistor is inside the circuit.

STLC5465B

67/101

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