STLC60135 datasheet(10/25 Pages) STMICROELECTRONICS

10 / 25 page

this specification are also supported.

The data received from the demapper may be

split into two paths, one dedicated to an inter-

leaved data flow the other one for a fast data

flow. No external RAM is needed for the inter-

leaved path.

The interleaving/deinterleaving is used to in-

crease the error correcting capability of block

codes for error bursts. After deinterleaving (if ap-

plicable), the data flow enters a Reed-Solomon

error correcting code decoder, able to correct a

number of bytes containing bit errors. The de-

coder also uses the information of previous re-

ceiving stages that may have detected the er-

rored bytes and have labelled them with an

“erasure” indication”.

Each time the RS decoder detects and corrects

errors in a RS codeword, an RS correction event

is generated. The occurrence of such events can

be signalled to the management layer.

After the RS decoder, the corrected byte stream

is descrambled in the PMD (Physical Medium De-

pendent) descramblers.

Two descramblers are used, for interleaved and

non-interleaved data flows.

These are defined in ANSI T1.413.

After descrambling, the data flows enter the De-

framer that extracts and processes bytes to sup-

port Physical layer related functions according to

ANSI T1.413. The ADSL frames indeed contain

physical layer-related information in addition to

the data passed to the higher layers. In particular,

the deframer extracts the EOC (Embedded Op-

erations Channel), the AOC (ADSL Overhead

Control) and the indicators bits and passes them

to the appropriate processing unit (e.g. the trans-

ceiver controller). The deframer also performs a

CRC check (Cyclic Redundancy Check ) on the

received frame and generates events in case of

error detection.

Event counters can be read by management

processes. The outputs of the deframer are an in-

terleaved and a fast data streams.

These data streams can either carry ATM cells or

another type of traffic. In the latter case, the ATM

specific TC layer functional block, described here-

after, is bypassed and the data stream is directly

presented at the input of the interface module.

ATM Specific TC Layer Functions

The 2 bytes streams (fast and slow) are received

from the byte-based processing unit. When ATM

cells are transported, this block provides basic

cell functions such as cell synchronization, cell

payload descrambling, idle/unassigned cell filter,

cell Header Error Correction (HEC) and detection.

The cell processing happens according to ITU-T

I.163 standard. Provision is also made for BER

measurements at this ATM cell level. When non

cell oriented byte streams are transported, the

cell processing unit is not active. The interface

module collects cells (from the cell-based function

module) or a Byte stream (from the deframer).

Cells are stored in FIFO’s (424 bytes or 8 cell

wide, transmit buffers have the same size), from

which they are extracted by 2 interface sub-

modules, one providing a Utopia level 1 interface

and the other a Utopia level 2 interface.

Byte stream are dumped on the SLAP (Synchro-

nous Link Access Protocol) interface.

Only one type of interface can be enabled in a

specific configuration.

DMT Symbol Timing Unit (DSTU)

The DSTU interfaces with various modules, like

DSP FrontEnd, FFT/IFFT, Mapper/Demapper,

RS , Monitor and Transceiver Controller. It con-

sists of a real time and a scheduler modules. The

real time unit generate a timebase for the DMT

symbols (sample counter), superframes (symbol

counter) and hyper-frames (sync counter). The

timebases can be modified by various control fea-

tures. They are continuously fine-tuned by the

DPLL module.

CELL

SCRAMBLER

DESCRAMBLER

SYNCHRONIZER

INTERFACE

MODULE

FROM

GENERIC

D98TL318A

FAST

SLOW

HEC

CELL

SCRAMBLER

DESCRAMBLER

SYNCHRONIZER

CELL

INSERTION/

FILTER

BER

CELL

INSERTION/

FILTER

Figure 7. ATM Specific TC Layer Functions

UTOPIA

FROM

ATM TC

D98TL319A

LEVEL

UTOPIA

LEVEL

UTOPIA

LEVEL

UTOPIA

LEVEL

FAST ATM

SLOW ATM

SLAP

SLOW BYTE STREAM

FAST BYTE STREAM

Figure 8. Interface Module

STLC60135

10/25

STLC60135 Datasheet(PDF) 10 Page - STMicroelectronics

STLC60135 Datasheet(HTML) 10 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Datasheet Download

Link URL