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STLC60135 Datasheet(PDF) 13 Page - STMicroelectronics |
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STLC60135 Datasheet(HTML) 13 Page - STMicroelectronics |
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13 / 25 page  Generic Processor Interface Pins and Func- tional Description Name Type Function AD[0..15] I/O Multiplexed address / data bus ALE I Address Latch Enable RDB I Read cycle indication WRB I Write cycle indication CSB I Chip Select RDYB OZ Bus cycle ready indication INTB O Interrupt Digital interface ATM or serial Digital Interface for data to the loop before modu- lation and from the loop after demodulation. This interface collects cells (from the cell based func- tion module) or a byte stream (from the deframer). Cells are stored in a fifo, 2 interfaces submodules can extract data from the fifo. Byte streams are dumped on the bitstream interface (with no fifo). 3 kinds of interface are allowed Utopia Level 1 Utopia Level 2 Bitstream based on a proprietary exchange The interface selection is programmed by writing the Utopia PHY address register. Only one interface can be enabled in a ST60135 configuration. Utopia Level 1 supports only one PHY device. Utopia Level 2 supports multi-PHY devices (See Utopia Level 2 specifications). Each buffer provides storage for 8 ATM cells (both directions for Fast and Interleaved channel). Talew D98TL326 ALE AD(15:0) Tavs Tavh Figure 14. Waveforms Symbol Parameters Min Typ Max Unit tr & tf Rise & Fall time (10% to 90%) 3 ns Talew ALE pulse width 12 ns Tavs Address Valid setup time 10 ns Tavh Address Valid Hold time 10 ns Tale2cs ALE to CSB 0 ns Tale2Z ALE to high Z state of address bus 50 ns Tcs2rdy CSB to RDYB asserted 60 ns Tcsre Access Time 900 µs Tcs2wr CSB to WRB 0 ns Twr2d WRB to data 15 ns Trdy2wr RDYB to WRB 0 ns Tdvs data setup time 10 ns Tdvh data hold time 1/2Tmclk Tmclk ns Twr2cs WRB to CSB -10 ns Tcs2rd CSB to RDB 0 ns Trdy2rd RDY to RDB 0 ns Trd2cs RDB to CSB -10 ns Tmclk Master clock Timing Generic processor interface Cycle Timing All AC characteristics are indicated for a 100pF capacitive load. STLC60135 13/25 |
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