Electrical Characteristics

MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semiconductor

17

2.5.3

Clock and Timing Signals

The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for

frequency values are not exceeded.

Table 7. Maximum Frequencies

Characteristic

Maximum in MHz

Core frequency

300/400

Reference frequency (REFCLK)

100/133

Internal bus frequency (BLCK)

100/133

DSI clock frequency (HCLKIN)

•

Core frequency = 300 MHz

•

Core frequency = 400 MHz

HCLKIN

≤ (min{70 MHz, CLKOUT})

HCLKIN

≤ (min{100 MHz, CLKOUT})

External clock frequency (CLKIN or CLKOUT)

100/133

Table 8. Clock Frequencies

Characteristics

Symbol

300 MHz Device

400 MHz Device

MinMax

MinMax

CLKIN frequency

20

100

20

133.3

BCLK frequency

40

100

40

133.3

Reference clock (REFCLK) frequency

40

100

40

133.3

Output clock (CLKOUT) frequency

40

100

40

133.3

SC140 core clock frequency

200

300

200

400

Note:

The rise and fall time of external clocks should be 3 ns maximum

Table 9. System Clock Parameters

Characteristic

Min

Max

Unit

Phase jitter between BCLK and CLKIN

—

0.3

ns

CLKIN frequency

20

see Table 8

MHz

CLKIN slope

—3

ns

PLL input clock (after predivider)

20

100

MHz

Time

o.5 V

3.3 V

1.1 V

PORESET/TRST asserted

CLKIN starts toggling

PORESET/TRST deasserted

1