38K2 datasheet(13/358 Pages) RENESAS

13 / 358 page

Rev.2.00

Oct 15, 2006

page 9 of 14

38K2 Group

REJ09B0338-0200

List of figures

Fig. 2.8.1 Memory map of registers related to A/D converter .................................................. 72

Fig. 2.8.2 Structure of AD control register .................................................................................. 72

Fig. 2.8.3 Structure of AD conversion register 1 ....................................................................... 73

Fig. 2.8.4 Structure of AD conversion register 2 ....................................................................... 73

Fig. 2.8.5 Structure of Interrupt request register 2 .................................................................... 74

Fig. 2.8.6 Structure of Interrupt control register 2 ..................................................................... 74

Fig. 2.8.7 Connection diagram ...................................................................................................... 75

Fig. 2.8.8 Related registers setting .............................................................................................. 75

Fig. 2.8.9 Control procedure for 8-bit read ................................................................................. 76

Fig. 2.8.10 Control procedure for 10-bit read ............................................................................. 76

Fig. 2.9.1 Memory map of registers related to watchdog timer ............................................... 78

Fig. 2.9.2 Structure of Watchdog timer control register ............................................................ 78

Fig. 2.9.3 Structure of CPU mode register ................................................................................. 79

Fig. 2.9.4 Watchdog timer connection and division ratio setting ............................................. 80

Fig. 2.9.5 Related registers setting .............................................................................................. 81

Fig. 2.9.6 Control procedure .......................................................................................................... 81

Fig. 2.10.1 Example of poweron reset circuit ............................................................................. 82

Fig. 2.10.2 RAM backup system ................................................................................................... 82

Fig. 2.11.1 Memory map of registers related to PLL ................................................................. 84

Fig. 2.11.2 Structure of USB control register ............................................................................. 84

Fig. 2.11.3 Structure of CPU mode register ............................................................................... 85

Fig. 2.11.4 Structure of PLL control register .............................................................................. 85

Fig. 2.11.5 Block diagram for frequency synthesizer circuit ..................................................... 86

Fig. 2.11.6 Related registers setting when hardware reset ...................................................... 87

Fig. 2.11.7 Related registers setting when stop mode .............................................................. 88

Fig. 2.11.8 Related registers setting when recovery from stop mode .................................... 89

Fig. 2.12.1 Memory map of registers related to clock generating circuit ............................... 90

Fig. 2.12.2 Structure of USB control register ............................................................................. 90

Fig. 2.12.3 Structure of CPU mode register ............................................................................... 91

Fig. 2.12.4 Structure of PLL control register .............................................................................. 91

Fig. 2.12.5 Related registers setting ............................................................................................ 92

Fig. 2.12.6 Related registers setting ............................................................................................ 94

Fig. 2.13.1 Memory map of registers related to standby function ........................................... 95

Fig. 2.13.2 Structure of MISRG .................................................................................................... 95

Fig. 2.13.3 Oscillation stabilizing time at restoration by reset input ....................................... 97

Fig. 2.13.4 Execution sequence example at restoration by occurrence of INT0 interrupt request

...................................................................................................................................... 99

Fig. 2.13.5 Reset input time ........................................................................................................ 101

Fig. 2.14.1 Memory map of flash memory version for 38K2 Group ...................................... 103

Fig. 2.14.2 Memory map of registers related to flash memory .............................................. 104

Fig. 2.14.3 Structure of Flash memory control register ........................................................... 104

Fig. 2.14.4 Rewrite example of built-in flash memory in standard serial I/O mode ............ 107

Fig. 2.14.5 Connection example in standard serial I/O mode (1) .......................................... 108

Fig. 2.14.6 Connection example in standard serial I/O mode (2) .......................................... 108

Fig. 2.14.7 Connection example in standard serial I/O mode (3) .......................................... 109

Fig. 2.14.8 Example of rewrite system for built-in flash memory in CPU rewrite mode .... 110

Fig. 2.14.9 CPU rewrite mode beginning/release flowchart .................................................... 111

CHAPTER 3 APPENDIX

Fig. 3.1.1 Output switching characteristics measurement circuit ............................................. 11

Fig. 3.1.2 USB output switching characteristics measurement circuit (1) for D0-, D1+/D2+ (low-speed),

D1-/D2- (full-speed) ....... 13

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