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H8SX/1663 Datasheet(PDF) 887 Page - Renesas Technology Corp |
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H8SX/1663 Datasheet(HTML) 887 Page - Renesas Technology Corp |
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887 / 1158 page  Section 17 I 2C Bus Interface 2 (IIC2) Rev.1.00 Jun. 07, 2006 Page 835 of 1102 REJ09B0294-0100 SDA (Master output) SDA (Slave output) TDRE TEND ICDRT ICDRS 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 21 2 34 56 78 9 A R/W SCL (Master output) Slave address Address + R/W Data 1 Data 2 Address + R/W Data 1 [2] Instruction of start condition issuance [3] Write data to ICDRT (first byte) [4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte) User processing Figure 17.5 Master Transmit Mode Operation Timing 1 SDA (Master output) SDA (Slave output) TDRE TEND ICDRT ICDRS 1 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 23 4 5 67 8 9 A A/A SCL (Master output) Data n Data n [7] Set slave receive mode [5] Write data to ICDRT [6] Issue stop condition. Clear TEND. User processing Figure 17.6 Master Transmit Mode Operation Timing 2 |
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