H8SXSLASH1663 datasheet(883/1158 Pages) RENESAS

883 / 1158 page

Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 831 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

ADZ

R/W

General Call Address Recognition Flag

This bit is valid in slave receive mode.

[Setting condition]

• When the general call address is detected in slave

receive mode

[Clearing condition]

• When 0 is written to this bit after reading ADZ = 1

(When the CPU is used to clear this flag by writing

0 while the corresponding interrupt is enabled, be

sure to read the flag after writing 0 to it.)

17.3.6

Slave Address Register (SAR)

SAR is sets the slave address. In slave mode, if the upper 7 bits of SAR match the upper 7 bits of

the first frame received after a start condition, the LSI operates as the slave device.

Bit

Bit Name

Initial Value

R/W

SVA6

R/W

SVA5

R/W

SVA4

R/W

SVA3

R/W

SVA2

R/W

SVA1

R/W

SVA0

R/W



R/W

Bit

Bit Name

Initial

Value

R/W

Description

7 to 1

SVA6 to

SVA0

R/W

Slave Address 6 to 0

These bits set a unique address differing from the

addresses of other slave devices connected to the I

bus.



R/W

Reserved

Although this bit is readable/writable, only 0 should be

written to.

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