H8SXSLASH1663 datasheet(885/1158 Pages) RENESAS

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Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 833 of 1102

REJ09B0294-0100

17.4

Operation

17.4.1

2C Bus Format

Figure 17.3 shows the I

2C bus formats. Figure 17.4 shows the I2C bus timing. The first frame

following a start condition always consists of 8 bits.

SLA

DATA

(a) I2C bus format

(b) I2C bus format (start condition retransmission)

n: Transfer bit count

(n = 1 to 8)

m: Transfer frame count

≥ 1)

SLA

DATA

SLA

DATA

n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)

m1 and m2: Transfer frame count (m1 and m2

≥ 1)

Figure 17.3 I

2C Bus Formats

SDA

SCL

SLA

1-7

DATA

Figure 17.4 I

2C Bus Timing

[Legend]

Start condition. The master device drives SDA from high to low while SCL is high.

SLA:

Slave address

Indicates the direction of data transfer; from the slave device to the master device when

W is 1, or from the master device to the slave device when R/W is 0.

Acknowledge. The receive device drives SDA low.

DATA: Transferred data

Stop condition. The master device drives SDA from low to high while SCL is high.

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