H8SXSLASH1663 datasheet(880/1158 Pages) RENESAS

880 / 1158 page

Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 828 of 1102

REJ09B0294-0100

17.3.5

2C Bus Status Register (ICSR)

ICSR confirms the interrupt request flags and status.

Bit

Bit Name

Initial Value

R/W

TDRE

R/W

TEND

R/W

RDRF

R/W

NACKF

R/W

STOP

R/W

AAS

R/W

ADZ

R/W

Bit

Bit Name

Initial

Value

R/W

Description

TDRE

R/W

Transmit Data Register Empty

[Setting condition]

• When data is transferred from ICDRT to ICDRS

and ICDRT becomes empty

[Clearing conditions]

• When 0 is written to this bit after reading TDRE = 1

(When the CPU is used to clear this flag by writing

0 while the corresponding interrupt is enabled, be

sure to read the flag after writing 0 to it.)

• When data is written to ICDRT

TEND

R/W

Transmit End

[Setting condition]

• When the ninth clock of SCL rises while the TDRE

flag is 1

[Clearing conditions]

• When 0 is written to this bit after reading TEND = 1

(When the CPU is used to clear this flag by writing

0 while the corresponding interrupt is enabled, be

sure to read the flag after writing 0 to it.)

• When data is written to ICDRT

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