H8SXSLASH1663 datasheet(1026/1158 Pages) RENESAS

1026 / 1158 page

Section 23 Power-Down Modes

Rev.1.00 Jun. 07, 2006 Page 974 of 1102

REJ09B0294-0100

23.2.1

Standby Control Register (SBYCR)

SBYCR controls software standby mode.

Bit

Bit Name

Initial Value

R/W

SSBY

R/W

OPE

R/W



R/W

STS4

R/W

STS3

R/W

STS2

R/W

STS1

R/W

STS0

R/W

Bit

Bit Name

Initial Value

R/W

SLPIE

R/W



R/W



R/W



R/W



R/W



R/W



R/W



R/W

Bit

Bit Name

Initial

Value

R/W

Description

SSBY

R/W

Software Standby

Specifies the transition mode after executing the SLEEP

instruction

0: Shifts to sleep mode after the SLEEP instruction is

executed

1: Shifts to software standby mode after the SLEEP

instruction is executed

This bit does not change when clearing the software

standby mode by using external interrupts and shifting to

normal operation. For clearing, write 0 to this bit. When

the WDT is used as the watchdog timer, the setting of this

bit is disabled. In this case, a transition is always made to

sleep mode or all-module-clock-stop mode after the

SLEEP instruction is executed. When the SLPIE bit is set

to 1, this bit should be cleared to 0.

OPE

R/W

Output Port Enable

Specifies whether the output of the address bus and bus

control signals (

CS0 to CS7, AS, RD, HWR, and LWR) is

retained or set to the high-impedance state in software

standby mode.

0: In software standby mode, address bus and bus

control signals are high-impedance

1: In software standby mode, address bus and bus

control signals retain output state

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