H8SXSLASH1663 datasheet(1024/1158 Pages) RENESAS

1024 / 1158 page

Section 23 Power-Down Modes

Rev.1.00 Jun. 07, 2006 Page 972 of 1102

REJ09B0294-0100

Table 23.1 shows conditions to shift to a power-down mode, states of the CPU and peripheral

modules, and clearing method for each mode. After the reset state, since this LSI operates in

normal program execution state, the modules, other than the DMAC and DTC are stopped.

Table 23.1

Operating States

Operating State

Sleep Mode

All-Module-Clock-

Stop Mode

Software Standby

Mode

Hardware

Standby Mode

Transition

condition

Control register +

instruction

Control register +

instruction

Control register +

instruction

Pin input

Cancellation

method

Interrupt

Interrupt*

Oscillator

Functioning

Halted

Subclock oscillator Functioning*

Functioning*

Halted

CPU

Halted (retained)

Halted

Watchdog timer

Functioning

Halted (retained)

Halted

8-bit timer

Functioning

Functioning*

Halted (retained)

Halted

32K timer

Functioning

Halted

Peripheral

modules

Functioning

Halted*

I/O port

Functioning

Retained

Hi-Z

Notes: "Halted (retained)" in the table means that the internal register values are retained and

internal operations are suspended.

1. SCI enters the reset state, and other peripheral modules retain their states.

2. External interrupt and some internal interrupts (8-bit timer, watchdog timer, and 32K

timer)

3. All peripheral modules enter the reset state.

4. "Functioning" or "Halted" is selectable through the setting of bits MSTPA9 and MSTPA8

in MSTPCRA. However, pin output is disabled even when "Functioning" is selected.

5. External interrupt and 32K timer interrupt

6. "Functioning" or "Halted" is selectable through the setting of bit OSC32STP in TCR32K.

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