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H8SX/1663R Datasheet(PDF) 888 Page - Renesas Technology Corp |
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H8SX/1663R Datasheet(HTML) 888 Page - Renesas Technology Corp |
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888 / 1504 page  Section 18 Watchdog Timer (WDT) Rev. 2.00 Sep. 24, 2008 Page 856 of 1468 REJ09B0412-0200 Overflow Interrupt control WOVI (interrupt request signal) Internal reset signal* WDTOVF Reset control RSTCSR TCNT TCSR P φ/2 P φ/64 P φ/128 P φ/512 P φ/2048 P φ/8192 P φ/32768 P φ/131072 Clock Clock select Internal clocks Bus interface Module bus TCSR: TCNT: RSTCSR: Note: * An internal reset signal can be generated by the RSTCSR setting. Timer control/status register Timer counter Reset control/status register WDT [Legend] Figure 18.1 Block Diagram of WDT 18.2 Input/Output Pin Table 18.1 shows the WDT pin configuration. Table 18.1 Pin Configuration Name Symbol I/O Function Watchdog timer overflow* WDTOVF Output Outputs a counter overflow signal in watchdog timer mode Note: * In boundary scan valid mode, counter overflow signal output cannot be used. |
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