H8SXSLASH1663R datasheet(892/1504 Pages) RENESAS

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Section 18 Watchdog Timer (WDT)

Rev. 2.00 Sep. 24, 2008 Page 860 of 1468

REJ09B0412-0200

18.4

Operation

18.4.1

Watchdog Timer Mode

To use the WDT in watchdog timer mode, set both the WT/

IT and TME bits in TCSR to 1.

During watchdog timer operation, if TCNT overflows without being rewritten because of a system

crash or other error, the

WDTOVF signal is output. This ensures that TCNT does not overflow

while the system is operating normally. Software must prevent TCNT overflows by rewriting the

TCNT value (normally H'00 is written) before overflow occurs. This

WDTOVF signal can be used

to reset the LSI internally in watchdog timer mode.

If TCNT overflows when the RSTE bit in RSTCSR is set to 1, a signal that resets this LSI

internally is generated at the same time as the

WDTOVF signal. If a reset caused by a signal input

to the

RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset

has priority and the WOVF bit in RSTCSR is cleared to 0.

The

WDTOVF signal is output for 133 cycles of Pφ when RSTE = 1 in RSTCSR, and for 130

cycles of P

φ when RSTE = 0 in RSTCSR. The internal reset signal is output for 519 cycles of Pφ.

When RSTE = 1, an internal reset signal is generated. Since the system clock control register

(SCKCR) is initialized, the multiplication ratio of P

φ becomes the initial value.

When RSTE = 0, an internal reset signal is not generated. Neither SCKCR nor the multiplication

ratio of P

φ is changed.

When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT

overflows when the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the

entire LSI.

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