H8SXSLASH1663R datasheet(891/1504 Pages) RENESAS

891 / 1504 page

Section 18 Watchdog Timer (WDT)

Rev. 2.00 Sep. 24, 2008 Page 859 of 1468

REJ09B0412-0200

18.3.3

Reset Control/Status Register (RSTCSR)

RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects

the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the

RES pin,

but not by the WDT internal reset signal caused by WDT overflows.

WOVF

R/(W)*

RSTE

R/W



R/W



Bit

Bit Name

Initial Value

R/W

Note: * Only 0 can be written to this bit, to clear the flag.

Bit

Bit Name

Initial

Value

R/W

Description

WOVF

R/(W)* Watchdog Timer Overflow Flag

This bit is set when TCNT overflows in watchdog timer

mode. This bit cannot be set in interval timer mode, and

only 0 can be written.

[Setting condition]

When TCNT overflows (changed from H'FF to H'00) in

watchdog timer mode

[Clearing condition]

Reading RSTCSR when WOVF = 1, and then writing 0 to

WOVF

RSTE

R/W

Reset Enable

Specifies whether or not this LSI is internally reset if

TCNT overflows during watchdog timer operation.

0: LSI is not reset even if TCNT overflows (Though this

LSI is not reset, TCNT and TCSR in WDT are reset)

1: LSI is reset if TCNT overflows



R/W

Reserved

Although this bit is readable/writable, reading from or

writing to this bit does not affect operation.

4 to 0



All 1

Reserved

These are read-only bits and cannot be modified.

Note:

Only 0 can be written to this bit, to clear the flag.

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