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H8SX/1663R Datasheet(PDF) 969 Page - Renesas Technology Corp

Part # H8SX/1663R
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Datasheet(HTML) 969 Page - Renesas Technology Corp

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Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Rev. 2.00 Sep. 24, 2008 Page 937 of 1468
REJ09B0412-0200
19.7.2
Data Format (Except in Block Transfer Mode)
Figure 19.25 shows the data transfer formats in smart card interface mode.
• One frame contains 8-bit data and a parity bit in asynchronous mode.
• During transmission, at least 2 etu (elementary time unit: time required for transferring one bit)
is secured as a guard time after the end of the parity bit before the start of the next frame.
• If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu
has passed from the start bit.
• If an error signal is sampled during transmission, the same data is automatically re-transmitted
after at least 2 etu.
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
In normal transmission/reception
Output from the transmitting station
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
When a parity error is generated
Output from the transmitting station
DE
Output from
the receiving station
[Legend]
Ds:
Start bit
D0 to D7: Data bits
Dp:
Parity bit
DE:
Error signal
Figure 19.25 Data Formats in Normal Smart Card Interface Mode
For communication with the smart cards of the direct convention and inverse convention types,
follow the procedure below.
Ds
AZ
Z
A
Z
Z
Z
ZA
A
(Z)
(Z) state
D0
D1
D2
D3
D4
D5
D6
D7
Dp
Figure 19.26 Direct Convention (SDIR = SINV = O/
E = 0)



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