H8SXSLASH1663R datasheet(971/1504 Pages) RENESAS

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Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 939 of 1468

REJ09B0412-0200

19.7.4

Receive Data Sampling Timing and Reception Margin

Only the internal clock generated by the on-chip baud rate generator can be used as a transfer

clock in smart card interface mode. In this mode, the SCI can operate on a base clock with a

frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 bit settings

(the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the

falling edge of the start bit is sampled using the base clock in order to perform internal

synchronization. Receive data is sampled on the 16th, 32nd, 186th and 128th rising edges of the

base clock so that it can be latched at the middle of each bit as shown in figure 19.28. The

reception margin here is determined by the following formula.

M = | (0.5 –

) – (L – 0.5) F –

+ F ) | × 100%

| D – 0.5 |

M: Reception margin (%)

N: Ratio of bit rate to clock (N = 32, 64, 372, 256)

D: Duty cycle of clock (D = 0 to 1.0)

L: Frame length (L = 10)

F: Absolute value of clock frequency deviation

[Legend]

Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is

determined by the formula below.

M =

( 0.5 –

) × 100%

= 49.866%

2 × 372

Internal

basic clock

372 clock cycles

186 clock

cycles

Receive data

(RxD)

Synchronization

sampling timing

Data sampling

timing

185

371 0

371

185

Start bit

Figure 19.28 Receive Data Sampling Timing in Smart Card Interface Mode

(When Clock Frequency is 372 Times the Bit Rate)

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