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H8SX/1663R Datasheet(PDF) 977 Page - Renesas Technology Corp

Part # H8SX/1663R
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Datasheet(HTML) 977 Page - Renesas Technology Corp

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Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Rev. 2.00 Sep. 24, 2008 Page 945 of 1468
REJ09B0412-0200
Initialization
Read data from RDR and
clear RDRF flag in SSR to 0
Clear RE bit in SCR to 0
Start reception
Start
Error processing
No
No
No
Yes
Yes
ORER = 0
and PER = 0?
RDRF = 1?
All data received?
Yes
Figure 19.33 Sample Reception Flowchart
19.7.8
Clock Output Control (Only SCI_0, 1, 2, and 4)
Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set
to 1. Specifically, the minimum width of a clock pulse can be specified.
Figure 19.34 shows an example of clock output fixing timing when the CKE0 bit is controlled
with GM = 1 and CKE1 = 0.
Given pulse width
SCK
CKE0
Given pulse width
Figure 19.34 Clock Output Fixing Timing



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