H8SXSLASH1663R datasheet(1203/1504 Pages) RENESAS

1203 / 1504 page

Section 25 Flash Memory

Rev. 2.00 Sep. 24, 2008 Page 1171 of 1468

REJ09B0412-0200

Figure 25.20 shows an example of overlaying flash memory block area EB0.

This area can be accessed via

both the on-chip RAM and flash

memory area.

Flash memory

user MAT

EB8 to EB15*1

On-chip RAM

H'00000

H'01000

H'02000

H'03000

H'04000

H'05000

H'06000

H'07000

H'08000

Notes:

EB8 to EB13 in the H8SX/1663.

EB8 to EB23 in the H8SX/1668.

H'05FFFF in the H8SX/1663.

H'0FFFFF in the H8SX/1668.

H'7FFFF*2

H'FF6000

H'FFA000

H'FFAFFF

H'FFBFFF

EB0

EB1

EB2

EB3

EB4

EB5

EB6

EB7

Figure 25.20 Address Map of Overlaid RAM Area (H8SX/1664)

The flash memory area that can be emulated is the one area selected by bits RAM2 to RAM0 in

RAMER from among the eight blocks, EB0 to EB7, of the user MAT.

To overlay a part of the on-chip RAM with block EB0 for realtime emulation, set the RAMS bit in

RAMER to 1 and bits RAM2 to RAM0 to B'000.

For programming/erasing the user MAT, the procedure programs including a download program

of the on-chip program must be executed. At this time, the download area should be specified so

that the overlaid RAM area is not overwritten by downloading the on-chip program. Since the area

in which the tuned data is stored is overlaid with the download area when FTDAR = H'01, the

tuned data must be saved in an unused area beforehand.

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