H8SXSLASH1663R datasheet(1302/1504 Pages) RENESAS

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Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1270 of 1468

REJ09B0412-0200

28.8.4

φ/SDRAMφ Operation after Exit from Deep Software Standby Mode

When the IOKEEP bit is 0, B

φ/SDRAMφ output is undefined for a maximum of one cycle

immediately after exit from deep software standby mode. At this time, the output state cannot be

guaranteed. Even when the IOKEEP bit is set to 1, B

φ/SDRAMφ output is undefined for a

maximum of one cycle immediately after the IOKEEP bit is cleared to 0 after deep software

standby mode was canceled, and the output state cannot be guaranteed

However, clock can be normally output by canceling deep software standby mode with the

IOKEEP bit set to 1 and then controlling the B

φ/SDRAMφ οutput with the IOKEEP and PSTOP1

bits. Following procedure takes B

φ for example. (See figure 28.3)

1. Change the value of the PSTOP1 bit from 0 to 1 to fix the B

φ output at the high level (given

that the B

φ output was already fixed high).

2. Clear the IOKEEP bit to 0 to end retention of the B

φ state.

3. Clear the PSTOP1 bit to 0 to enable B

φ output.

In case of the SDRAM

φ, clock can be normally output by controlling the PSTOP0 bit instead of

the PSTOP1 bit in the same way as the procedure above mentioned. For the port state when the

IOKEEP bit is set to 1, see section 28.8.3, Pin State on Exit from Deep Software Standby Mode.

Deep software standby mode

Oscillator

NMI

Internal reset

Clock is undefined

IOKEEP

cleared

PSTOP1

set

IOKEEP

cleared

PSTOP1

cleared

When IOKEEP = 1, the clock can be normally output

by using the PSTOP1 bit.

When IOKEEP = 0

When IOKEEP = 1

(IOKEEP=1)

(1) B

φ output cannot be guaranteed.

(2) The procedure to guarantee B

φ output is used.

Figure 28.3 B

φ Operation after Exit from Deep Software Standby Mode

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