H8SXSLASH1663R datasheet(1298/1504 Pages) RENESAS

1298 / 1504 page

Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1266 of 1468

REJ09B0412-0200

28.8

Deep Software Standby Mode

28.8.1

Entry to Deep Software Standby Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR has been set to 1, a transition to

software standby mode is made. In this state, if the CPSBY bit in DPSBYCR is set to 1, a

transition to deep software standby mode is made.

If a software standby mode clearing source (an NMI, IRQ0 to IRQ11, 32K timer, voltage-

monitoring interrupt requests*, or USB suspend/resume) occurs when a transition to software

standby mode is made, software standby mode will be cleared regardless of the DPSBY bit

setting, and the interrupt exception handling starts after the oscillation settling time for software

standby mode specified by the bits STS4 to STS0 in SBYCR has elapsed.

When both of the SSBY bit in SBYCR and the CPSBY bit in DPSBYCR are set to 1 and no

software standby mode clearing source occurs, a transition to deep software standby mode will be

made immediately after software standby mode is entered.

In deep software standby mode, the CPU, on-chip peripheral functions (except for the USB and

32K timer), on-chip RAMs 6 to 4, and oscillator functionality are all stopped. In addition, the

internal power supply to these modules stops, resulting in a significant reduction in power

consumption. At this time, the contents of all the registers of the CPU, on-chip peripheral

functions (except for the USB and 32K timer), and on-chip RAMs 6 to 4 become undefined.

Contents of the on-chip RAMs 3 to 0 and USB registers can be retained when all the bits

RAMCUT2 to RAMCUT0 in DPSBYCR have been cleared to 0. If these bits are set to all 1, the

internal power supply to the on-chip RAMs 3 to 0 and USB stops and the power consumption is

further reduced. At this time, the contents of the on-chip RAMs 3 to 0 and USB registers become

undefined.

The 32K timer, voltage detection circuit*, and power-on reset circuit* can be operated in deep

software standby mode.

The I/O ports can be retained in the same state as in software standby mode.

Note: * Supported only by the H8SX/1668M Group.

H8SX/1663R Datasheet(PDF) 1298 Page - Renesas Technology Corp