H8SXSLASH1663R datasheet(1299/1504 Pages) RENESAS

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Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1267 of 1468

REJ09B0412-0200

28.8.2

Exit from Deep Software Standby Mode

Exit from deep software standby mode is initiated by signals on the external interrupt pins (NMI

and

IRQ0-A to IRQ3-A), internal interrupt signals (32K timer, voltage-monitoring interrupt*, and

USB suspend/resume), voltage-monitoring interrupt reset*, power-on reset*,

RES pin, or STBY

pin.

1. Exit from deep software standby mode by external interrupt pins or internal interrupt signals

Deep software standby mode is canceled when any of the DNMIF, DIRQnF (n = 3 to 0),

DT32KIF, DLVDIF*, and DUSBIF bits in DPSIFR is set to 1. The DNMIF or DIRQnF (n = 3

to 0) bit is set to 1 when a specified edge is generated in the NMI or

IRQ0-A to IRQ3-A pins,

that has been enabled by the DIRQnE (n = 3 to 0) bit in DPSIER. The rising or falling edge of

the signals can be specified with DPSIEGR. The DT32KIF bit is set to 1 when a 32K timer

interrupt occurs. The DLVDIF bit is set to 1when a voltage-monitoring interrupt occurs. The

DUSBIF bit is set to 1 when a USB suspend/resume interrupt occurs.

When deep software standby mode clearing source is generated, internal power supply starts

simultaneously with the start of clock oscillation, and internal reset signal is generated for the

entire LSI. Once the time specified by the WTSTS5 to WTSTS0 bits in DPSWCR has elapsed,

a stable clock signal is being supplied throughout the LSI and the internal reset is cleared.

Deep software standby mode is canceled on clearing of the internal reset, and then the reset

exception handling starts.

When deep software standby mode is canceled by an external interrupt pin or internal interrupt

signal, the DPSRSTF bit in RSTSR is set to 1.

2. Exit from deep software standby mode by a voltage-monitoring reset*

When a voltage monitoring reset is generated by the power-supply voltage falling, the LSI is

released from deep software standby mode and clock oscillation starts. At the same time, a

clock signal is supplied throughout the LSI. When the power-supply voltage has risen

sufficiently, the LSI is released from the voltage-detection reset state. The CPU then starts

reset-exception handling.

3. Exit from power-on reset*

When a power-on reset is generated by the power-supply voltage falling, the LSI is released

from deep software standby mode. If the power-supply voltage then rises sufficiently, clock

oscillation starts and the LSI is released from the power-on reset state after the clock

oscillation stabilization time has been secured. As soon as the clock oscillation starts, the clock

signal is provided to the LSI. After that, the CPU starts reset-exception handling.

4. Exit from deep software standby mode by the signal on the

RES pin

H8SX/1663R Datasheet(PDF) 1299 Page - Renesas Technology Corp

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