H8SXSLASH1663R datasheet(1295/1504 Pages) RENESAS

1295 / 1504 page

Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1263 of 1468

REJ09B0412-0200

When a power-on reset is generated by the fall of power voltage, software standby mode is

released. After that, if power voltage rises, the clock oscillation starts and the power-on reset is

released while the clock oscillation stabilization time is well kept. Thereafter CPU starts the

reset exception handling.

4. Exit from software standby mode by

RES pin

When the

RES pin is driven low, clock oscillation is started. At the same time as clock

oscillation starts, clocks are supplied to the entire LSI. Note that the

RES pin must be held low

until clock oscillation settles. When the

RES pin goes high, the CPU begins reset exception

handling.

5. Exit from software standby mode by

STBY pin

When the

STBY pin is driven low, a transition is made to hardware standby mode.

Notes: 1. By setting the SSIn bit in SSIER to 1,

IRQ0 to IRQ11 can be used as a software

standby mode clearing source.

2. Supported only by the H8SX/1668M Group.

28.7.3

Setting Oscillation Settling Time after Exit from Software Standby Mode

Bits STS4 to STS0 in SBYCR should be set as described below.

1. Using a crystal resonator

Set bits STS4 to STS0 so that the standby time is at least equal to the oscillation settling time.

Table 28.2 shows the standby times for operating frequencies and settings of bits STS4 to

STS0.

2. Using an external clock

A PLL circuit settling time is necessary. Refer to table 28.2 to set the standby time.

H8SX/1663R Datasheet(PDF) 1295 Page - Renesas Technology Corp