H8SXSLASH1663R datasheet(1291/1504 Pages) RENESAS

1291 / 1504 page

Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1259 of 1468

REJ09B0412-0200

28.3

Multi-Clock Function

28.3.1

Switching of Main Clock Frequencies

When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, the clock

frequency is changed at the end of the bus cycle. The CPU and bus masters operate on the

operating clock specified by bits ICK2 to ICK0. The peripheral modules operate on the operating

clock specified by bits PCK2 to PCK0. The external bus operates on the operating clock specified

by bits BCK2 to BCK0.

Even if the frequencies specified by bits PCK2 to PCK0 and BCK2 to BCK0 are higher than the

frequency specified by bits ICK2 to ICK0, the specified values are not reflected in the peripheral

module and external bus clocks. The peripheral module and external bus clocks are restricted to

the operating clock specified by bits ICK2 to ICK0.

28.3.2

Switching to Subclock

When the CK32K bit in SUBCKCR is set to 1, a transition from the main clock operation to the

subclock operation is made at the end of the bus cycle regardless of the SCKCR setting. In the

subclock operation, the CPU, bus masters, peripheral modules, and all external buses operate on

the 32.768-kHz subclock.

When the CK32K bit in SUBCKCR is set to 0 in the subclock operation, a transition to the main

clock operation is made at the end of the bus cycle. Since a transition from the subclock operation

to the main clock operation is made via software standby mode, the oscillation settling time of the

main clock must elapse. Set the oscillation settling time of the main clock with bits STS4 to STS0

in SBYCR.

The main clock oscillator can be operated or stopped by the EXSTP bit in SUBCKCR in the

subclock operation. When a transition is made from the subclock operation to the main clock

operation with the main clock oscillator operating, the wait for the oscillation settling time of the

main clock oscillator is not necessary. A transition to the main clock operation can be made in the

minimum setting time with the setting of bits STS4 to STS0 in SBYCR.

In the same way as in the main clock operation, if a SLEEP instruction is executed in the subclock

operation while the SSBY bit in SBYCR is set to 1, this LSI enters software standby mode. When

a transition is made to software standby mode in the subclock operation, the operating clock of the

system clock after clearing of software standby mode can be selected with the WAKE32K bit in

SUBCKCR. This LSI is placed in the subclock operation if the WAKE32K bit is 1, or placed in

the main clock operation if the WAKE32K bit is 0.

H8SX/1663R Datasheet(PDF) 1291 Page - Renesas Technology Corp