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H8SX/1663R Datasheet(PDF) 1290 Page - Renesas Technology Corp |
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H8SX/1663R Datasheet(HTML) 1290 Page - Renesas Technology Corp |
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1290 / 1504 page ![]() Section 28 Power-Down Modes Rev. 2.00 Sep. 24, 2008 Page 1258 of 1468 REJ09B0412-0200 28.2.10 Deep Standby Backup Register (DPSBKRn) DPSBKRn (n = 15 to 0) is a 16-bit readable/writable register to store data during deep software standby mode. Although data in on-chip RAM is not retained in deep software standby mode, data in this register is retained. DPSBKRn (n = 15 to 0) is not initialized by the internal reset signal upon exit from deep software standby mode. Bit Bit name Initial value: R/W: 7 BKUPn7 0 R/W 6 BKUPn6 0 R/W 5 BKUPn5 0 R/W 4 BKUPn4 0 R/W 3 BKUPn3 0 R/W 2 BKUPn2 0 R/W 1 BKUPn1 0 R/W 0 BKUPn0 0 R/W n: 15 to 0 |
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