H8SXSLASH1663R datasheet(1286/1504 Pages) RENESAS

1286 / 1504 page

Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1254 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Module

DLVDIF*

R/(W)*

LVD Interrupt Flag

[Setting condition]

Voltage monitoring interrupt is generated.

[Clearing condition]

Writing a 0 to this bit after reading it as 1.

DIRQ3F

R/(W)*

IRQ3 Interrupt Flag

[Setting condition]

IRQ3-A input specified in DPSIEGR is generated.

[Clearing condition]

Writing a 0 to this bit after reading it as 1.

DIRQ2F

R/(W)*

IRQ2 Interrupt Flag

[Setting condition]

IRQ2-A input specified in DPSIEGR is generated.

[Clearing condition]

Writing a 0 to this bit after reading it as 1.

DIRQ1F

R/(W)*

IRQ1 Interrupt Flag

[Setting condition]

IRQ1-A input specified in DPSIEGR is generated.

[Clearing condition]

Writing a 0 to this bit after reading it as 1.

DIRQ0F

R/(W)*

IRQ0 Interrupt Flag

[Setting condition]

IRQ0-A input specified in DPSIEGR is generated.

[Clearing condition]

Writing a 0 to this bit after reading it as 1.

Note:

1. Only 0 can be written to clear the flag.

2. Supported only by the H8SX/1668M Group.

H8SX/1663R Datasheet(PDF) 1286 Page - Renesas Technology Corp

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