H8SXSLASH1663R datasheet(1282/1504 Pages) RENESAS

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Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1250 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Module

5 to 0

WTSTS

[5:0]

R/W

Deep Software Standby Wait Time Setting

These bits select the time for which the MCU waits until

the clock settles when deep software standby mode is

canceled by an interrupt.

When using a crystal resonator, see table 28.3 and select

the wait time greater than the oscillation settling time for

each operating frequency. When using an external clock,

settling time for the PLL circuit should be considered. See

table 28.3 to select the wait time.

During the oscillation settling period, counting is

performed with the clock frequency input to the EXTAL.

000000: Reserved

000001: Reserved

000010: Reserved

000011: Reserved

000100: Reserved

000101: Wait time = 64 states

000110: Wait time = 512 states

000111: Wait time = 1024 states

001000: Wait time = 2048 states

001001: Wait time = 4096 states

001010: Wait time = 16384 states

001011: Wait time = 32768 states

001100: Wait time = 65536 states

001101: Wait time = 131072 states

001110: Wait time = 262144 states

001111: Wait time = 524288 states

01xxxx: Reserved

[Legend]

x: Don't care

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