H8SXSLASH1663R datasheet(1279/1504 Pages) RENESAS

Part #	H8SX/1663R

Description	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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1279 / 1504 page

Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1247 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Module

DPSBY

R/W

Deep Software Standby

When the SSBY bit in SBYCR has been set to 1,

executing the SLEEP instruction causes a transition to

software standby mode. At this time, if there is no source

to clear software standby mode and this bit is set to 1, a

transition to deep software standby mode is made.

SSBY

DPSBY

Entry to

Enters sleep mode after

execution of a SLEEP instruction.

Enters software standby mode

after execution of a SLEEP

instruction.

Enters deep software standby

mode after execution of a SLEEP

instruction.

When deep software standby mode is canceled due to an

interrupt, this bit remains at 1. Write a 0 here to clear it.

Setting of this bit has no effect when the WDT is used in

watchdog timer mode. In this case, executing the SLEEP

instruction always initiates entry to sleep mode or all-

module-clock-stop mode. Be sure to clear this bit to 0

when setting the SLPIE bit to 1.

H8SX/1663R Datasheet(PDF) 1279 Page - Renesas Technology Corp