H8SXSLASH1663R datasheet(1275/1504 Pages) RENESAS

1275 / 1504 page

Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1243 of 1468

REJ09B0412-0200

• MSTPCRB

Bit

Bit name

Initial value:

R/W:

Bit

Bit name

Initial value:

R/W:

MSTPB15

R/W

MSTPB14

R/W

MSTPB13

R/W

MSTPB12

R/W

MSTPB11

R/W

MSTPB10

R/W

MSTPB9

R/W

MSTPB8

R/W

MSTPB7

R/W

MSTPB6

R/W

MSTPB5

R/W

MSTPB4

R/W

MSTPB3

R/W

MSTPB2

R/W

MSTPB1

R/W

MSTPB0

R/W

• MSTPCRA

Bit

Bit Name

Initial

Value

R/W

Module

ACSE

R/W

All-Module-Clock-Stop Mode Enable

Enables/disables all-module-clock-stop state for reducing

current consumption by stopping the bus controller and

I/O ports operations when the CPU executes the SLEEP

instruction after module stop state has been set for all the

on-chip peripheral modules controlled by MSTPCR.

0: All-module-clock-stop mode disabled

1: All-module-clock-stop mode enabled

MSTPA14

R/W

EXDMA controller (EXDMAC)

MSTPA13

R/W

DMA controller (DMAC)

MSTPA12

R/W

Data transfer controller (DTC)

MSTPA11

MSTPA10

R/W

Reserved

These bits are always read as 1. The write value should

always be 1.

MSTPA9

R/W

8-bit timer (TMR_3 and TMR_2)

MSTPA8

R/W

8-bit timer (TMR_1 and TMR_0)

MSTPA7

MSTPA6

R/W

Reserved

These bits are always read as 1. The write value should

always be 1.

H8SX/1663R Datasheet(PDF) 1275 Page - Renesas Technology Corp

H8SX/1663R Datasheet(HTML) 1275 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL