H8SXSLASH1663R datasheet(1271/1504 Pages) RENESAS

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Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1239 of 1468

REJ09B0412-0200

28.2

The registers related to the power-down modes are shown below. For details on the system clock

control register (SCKCR), refer to section 27.1.1, System Clock Control Register (SCKCR).

• Standby control register (SBYCR)

• Module stop control register A (MSTPCRA)

• Module stop control register B (MSTPCRB)

• Module stop control register C (MSTPCRC)

• Deep standby control register (DPSBYCR)

• Deep standby wait control register (DPSWCR)

• Deep standby interrupt enable register (DPSIER)

• Deep standby interrupt flag register (DPSIFR)

• Deep standby interrupt edge register (DPSIEGR)

• Reset status register (RSTSR)

• Deep standby backup register n (DPSBKRn) (n=15 to 0)

28.2.1

Standby Control Register (SBYCR)

SBYCR controls software standby mode.

Bit

Bit name

Initial value:

R/W:

Bit

Bit name

Initial value:

R/W:

SSBY

R/W

OPE

R/W



R/W

STS4

R/W

STS3

R/W

STS2

R/W

STS1

R/W

STS0

R/W

SLPIE

R/W



R/W



R/W



R/W



R/W



R/W



R/W



R/W

H8SX/1663R Datasheet(PDF) 1271 Page - Renesas Technology Corp

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