H8SXSLASH1663R datasheet(1274/1504 Pages) RENESAS

1274 / 1504 page

Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1242 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

SLPIE

R/W

Sleep Instruction Exception Handling Enable

Selects whether a sleep interrupt is generated or a

transition to power-down mode is made when a SLEEP

instruction is executed.

0: A transition to power-down mode is made when a

SLEEP instruction is executed.

1: A sleep instruction exception handling is generated

when a SLEEP instruction is executed.

Even after a sleep instruction exception handling is

executed, this bit remains set to 1. For clearing, write 0 to

this bit.

6 to 0



All 0

R/W

Reserved

These bits are always read as 0. The write value should

always be 0.

[Legend]

x: Don't care

Note:

With the F-ZTAT version, the flash memory settling time must be reserved.

28.2.2

Module Stop Control Registers A and B (MSTPCRA and MSTPCRB)

MSTPCRA and MSTPCRB control module stop state. Setting a bit to 1 makes the corresponding

module enter module stop state, while clearing the bit to 0 clears module stop state.

• MSTPCRA

Bit

Bit name

Initial value:

R/W:

Bit

Bit name

Initial value:

R/W:

ACSE

R/W

MSTPA14

R/W

MSTPA13

R/W

MSTPA12

R/W

MSTPA11

R/W

MSTPA10

R/W

MSTPA9

R/W

MSTPA8

R/W

MSTPA7

R/W

MSTPA6

R/W

MSTPA5

R/W

MSTPA4

R/W

MSTPA3

R/W

MSTPA2

R/W

MSTPA1

R/W

MSTPA0

R/W

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