H8SXSLASH1663R datasheet(1294/1504 Pages) RENESAS

1294 / 1504 page

Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1262 of 1468

REJ09B0412-0200

28.7

Software Standby Mode

28.7.1

Entry to Software Standby Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1 and the DPSBY bit in

DPSBYCR is cleared to 0, software standby mode is entered. In this mode, the CPU, on-chip

peripheral functions, and oscillator all stop. However, the contents of the CPU's internal registers,

on-chip RAM data, and the states of on-chip peripheral functions other than the SCI, and the states

of the I/O ports, are retained. Whether the address bus and bus control signals are placed in the

high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this

mode the oscillator stops, allowing power consumption to be significantly reduced.

If the WDT is used in watchdog timer mode, it is impossible to make a transition to software

standby mode. The WDT should be stopped before the SLEEP instruction execution.

28.7.2

Exit from Software Standby Mode

Software standby mode is cleared by an external interrupt (NMI, or

IRQ0 to IRQ11*1) or internal

interrupt (32K timer, voltage detection interrupt *

2, or USB suspend/resume), voltage-detection

reset*

2, power-on reset*2

RES pin or STBY pin.

1. Exit from software standby mode by interrupt

When an NMI, IRQ0 to IRQ11*

1, 32K-timer, or USB suspend/resume interrupt request signal

is input, clock oscillation starts, and after the elapse of the time set in bits STS4 to STS0 in

SBYCR, stable clocks are supplied to the entire LSI, software standby mode is cleared, and

interrupt exception handling is started.

When clearing software standby mode with an IRQ0 to IRQ11* interrupt, set the

corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts

IRQ0 to IRQ11*

1 is generated. Software standby mode cannot be cleared if the interrupt has

been masked on the CPU side or has been designated as a DTC activation source.

2. Exit from voltage monitoring reset*

When a voltage monitoring reset is generated by the fall of power-voltage, software standby

mode is cleared and a clock oscillation starts. At the same time, a clock signal is supplied

throughout the LSI. After that, if power voltage rises, the voltage detection reset is released.

Thereafter, CPU starts the reset exception handling.

3. Exit from power-on reset*

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