H8SXSLASH1663R datasheet(1293/1504 Pages) RENESAS

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Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1261 of 1468

REJ09B0412-0200

• Exit from sleep mode by reset caused by watchdog timer overflow

Sleep mode is exited by an internal reset caused by a watchdog timer overflow.

• Exit from voltage monitoring reset*

Sleep mode is exited by a voltage monitoring reset of the voltage detection circuit.

• Exit from power-on reset*

Sleep mode is exited by a power-on reset.

Note:

* Supported only by the H8SX/1668M Group.

28.6

All-Module-Clock-Stop Mode

When the ACSE bit is set to 1 and all modules controlled by MSTPCRA and MSTPCRB are

stopped (MSTPCRA, MSTPCRB = H'FFFFFFFF), or all modules except for the 8-bit timer (units

0 and 1) are stopped (MSTPCRA, MSTPCRB = H'F[C to F]FFFFFF), executing a SLEEP

instruction with the SSBY bit in SBYCR cleared to 0 will cause all modules (except for the 8-bit

timer*

1, watchdog timer, 32K timer, power-on reset circuit*2 and voltage detection circuit*2), the

bus controller, and the I/O ports to stop operating, and to make a transition to all-module-clock-

stop mode at the end of the bus cycle.

When power consumption should be reduced ever more in all-module-clock-stop mode, stop

modules controlled by MSTPCRC (MSTPCRC[15:8] = H'FFFF).

All-module-clock-stop mode is cleared by an external interrupt (NMI or

IRQ0 to IRQ11 pins),

RES pin input, or an internal interrupt (8-bit timer*1, watchdog timer, 32K timer, or voltage-

detection circuit*

2), and the CPU returns to the normal program execution state via the exception

handling state. All-module-clock-stop mode is not cleared if interrupts are disabled, if interrupts

other than NMI are masked on the CPU side, or if the relevant interrupt is designated as a DTC

activation source.

When the

STBY pin is driven low, a transition is made to hardware standby mode.

Notes: 1. Operation or halting of the 8-bit timer can be selected by bits MSTPA9 and MSTPA8

in MSTPCRA.

Supported only by the H8SX/1668M Group.

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