H8SXSLASH1663R datasheet(1307/1504 Pages) RENESAS

1307 / 1504 page

Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1275 of 1468

REJ09B0412-0200

(2)

Deep Software Standby Mode in External Extended Mode (IOKEEP = 1)

Figure 28.5 shows an example of operations in deep standby mode when the IOKEEP and OPE

bits are set to 1 in external extended mode.

In this example, deep software standby mode is entered with the IOKEEP and OPE bits set to 1,

and then exited at the rising edge of the NMI pin. In external expansion mode, while the IOKEEP

bit is set to 1, retention of the states of pins for the address bus, bus-control signals (

CS0, AS, RD,

HWR, and LWR), data bus is released after the oscillation settling time has elapsed. For other

pins, including the B

φ output pin, retention is released when the IOKEEP bit is cleared to 0, and

then they are set according to the I/O port or peripheral module settings.

Oscillator

NMI

SLEEP

instruction

Deep software standby mode

(power-down mode)

Program

execution state

Program

execution state

Reset

exception

handling

Oscillation

settling time

Internal reset

Operated

Retained

Address

Retained

Bus control

Retained

Data

Retained

PSTOP1

set

PSTOP1

cleared

IOKEEP cleared

Retained

I/O other than

above

Started from h'00000

Operated

Figure 28.5 Example of Deep Software Standby Mode Operation in

External Extended Mode (IOKEEP = OPE = 1)

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