H8SXSLASH1663R datasheet(1311/1504 Pages) RENESAS

1311 / 1504 page

Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1279 of 1468

REJ09B0412-0200

28.9

Hardware Standby Mode

28.9.1

Transition to Hardware Standby Mode

When the

STBY pin is driven low, a transition is made to hardware standby mode from any mode.

In hardware standby mode, all functions enter the reset state and stop operation, resulting in a

significant reduction in power consumption. Data in the on-chip RAM is not retained because the

internal power supply to the on-chip RAM stops. I/O ports are set to the high-impedance state.

Do not change the states of mode pins (MD3 to MD0) while this LSI is in hardware standby mode.

28.9.2

Clearing Hardware Standby Mode

Hardware standby mode is cleared by means of the

STBY pin and the RES pin. When the STBY

pin is driven high while the

RES pin is low, the reset state is entered and clock oscillation is

started. Ensure that the

RES pin is held low until clock oscillation settles (for details on the

oscillation settling time, refer to table 28.2). When the

RES pin is subsequently driven high, a

transition is made to the program execution state via the reset exception handling state.

28.9.3

Hardware Standby Mode Timing

Figure 28.8 shows an example of hardware standby mode timing.

When the

STBY pin is driven low after the RES pin has been driven low, a transition is made to

hardware standby mode. Hardware standby mode is cleared by driving the

STBY pin high,

waiting for the oscillation settling time, then changing the

RES pin from low to high.

Oscillator

RES

STBY

Oscillation

settling time

Reset exception

handling

Figure 28.8 Hardware Standby Mode Timing

H8SX/1663R Datasheet(PDF) 1311 Page - Renesas Technology Corp