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H8SX/1663R Datasheet(PDF) 1491 Page - Renesas Technology Corp |
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H8SX/1663R Datasheet(HTML) 1491 Page - Renesas Technology Corp |
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1491 / 1504 page ![]() Main Revisions and Additions in this Edition Rev. 2.00 Sep. 24, 2008 Page 1459 of 1468 REJ09B0412-0200 Item Page Revision (See Manual for Details) 29.2 Register Bits 1330 Added Register Abbreviati on Bit 31/23/1 5/7 Bit 30/22/1 4/6 Bit 29/21/1 3/5 Bit 28/20/1 2/4 Bit 27/19/1 1/3 Bit 26/18/1 0/2 Bit 25/17/9/ 1 Bit 24/16/8/ 0 Module LVDCR* 3 LVDE LVDRI LVDMO N SYSTE M Added due to the addition of the LVD. 29.3 Register States in Each Operating Mode 1351 Added Register Abbreviation Reset Module Stop State Slee p All- Module- Clock- Stop Softwar e Standb y Deep Software Standby Hardwar e Standby Module LVDCR* 3 Initialize d* 4 Initialized SYSTEM Added due to the addition of the LVD. Section 30 Electrical Characteristics 30.3 DC Characteristics, H8SX/1668M Group 1363 Added Replaced due to the addition of the H8SX/1668M Group. 30.4.AC Characteristics Figure 30.1 Output Load Circuit 1367 Added Note is added due to the addition of the H8SX/1668M Group. 30.4.1 Clock Timing 1367, 1368 Added Conditions and the note on Table 30.6 Clock Timing are added due to the addition of the H8SX/1668M Group. 30.4.2 Control Signal Timing 1370 Added Conditions and the note on Table 30.7 Control Signal Timing are added due to the addition of the H8SX/1668M Group. 30.4.3 Bus Timing 1371, 1372 Added Conditions and the note on Table 30.8 Bus Timing (1) to (4) are added due to the addition of the H8SX/1668M Group. |
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