H8SXSLASH1663R datasheet(1495/1504 Pages) RENESAS

1495 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page 1463 of 1468

REJ09B0412-0200

I/O ports.................................................. 595

I2C bus format....................................... 1050

I2C bus interface2 (IIC2) ...................... 1033

ID code ................................................... 923

Idle cycle ................................................ 347

Illegal instruction.................................... 126

Input buffer control register.................... 606

Input capture function............................. 734

Internal interrupts ................................... 148

Internal peripheral bus ............................ 220

Internal system bus ................................. 220

Interrupt .................................................. 123

Interrupt control mode 0 ......................... 156

Interrupt control mode 2 ......................... 158

Interrupt controller.................................. 129

Interrupt exception handling sequence ... 160

Interrupt exception handling vector

table ........................................................ 149

Interrupt response times.......................... 161

Interrupt sources ..................................... 147

Interrupt sources and vector address

offsets ..................................................... 149

Interrupt-in transfer............................... 1021

Interval timer .......................................... 862

Interval timer mode................................. 862

Inverse convention.................................. 938

IRQn interrupts ....................................... 147

JTAG interface ..................................... 1067

Little endian............................................ 232

Mark state ....................................... 912, 953

Master receive mode ............................. 1053

Master transmit mode ........................... 1051

MCU operating modes.............................. 79

Memory MAT configuration ................ 1110

Mode 2 ...................................................... 85

Mode 4 ...................................................... 85

Mode 5 ...................................................... 86

Mode 6 ...................................................... 86

Mode 7 ...................................................... 86

Mode pin ................................................... 79

Multi-clock mode.................................. 1259

Multiprocessor bit ................................... 923

Multiprocessor communication

function ................................................... 923

NMI interrupt.......................................... 147

Noise canceler....................................... 1059

Nonlinearity error.................................. 1090

Non-overlapping pulse output................. 801

Normal transfer mode ............................. 579

Normal transfer mode ..................... 406, 485

Number of access cycles ......................... 233

Offset addition ........................................ 418

Offset addition method ........................... 495

Offset error............................................ 1090

On-board programming ........................ 1138

On-board programming mode............... 1105

On-chip baud rate generator.................... 915

On-chip ROM disabled extended mode.... 79

On-chip ROM enabled extended mode..... 79

Open-drain control register ..................... 608

Oscillator............................................... 1227

Output buffer control .............................. 609

Output trigger.......................................... 800

Overflow ......................................... 836, 860

H8SX/1663R Datasheet(PDF) 1495 Page - Renesas Technology Corp

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