H8SXSLASH1663R datasheet(1493/1504 Pages) RENESAS

1493 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page 1461 of 1468

REJ09B0412-0200

Index

Numerics

0 output/1 output..................................... 733

0-output/1-output .................................... 733

16-bit access space.................................. 242

16-bit counter mode................................ 836

16-bit timer pulse unit (TPU) ................. 683

32K timer (TM32K) ............................... 845

8-bit access space.................................... 241

8-bit timers (TMR) ................................. 811

A/D conversion accuracy...................... 1090

Absolute accuracy................................. 1090

Acknowledge........................................ 1050

Address error .......................................... 120

Address map ............................................. 87

Address mode ......................................... 531

Address modes................................ 402, 482

Address/data multiplexed I/O

interface .......................................... 234, 270

All-module-clock-stop mode ...... 1236, 1261

Area 0 ..................................................... 236

Area 1 ..................................................... 237

Area 2 ..................................................... 237

Area 3 ..................................................... 238

Area 4 ..................................................... 238

Area 5 ..................................................... 239

Area 6 ..................................................... 239

Area 7 ..................................................... 240

Area division........................................... 229

Asynchronous mode ............................... 912

AT-cut parallel-resonance type............. 1227

Available output signal and settings in

each port ................................................. 653

Average transfer rate generator............... 868

φ clock output control.........................1284

Basic bus interface .......................... 233, 244

Big endian ............................................... 232

Bit rate..................................................... 895

Bit synchronous circuit ......................... 1064

Block structure...................................... 1111

Block transfer mode................ 408, 487, 582

Boot mode................................... 1108, 1139

Boundary scan commands .................... 1209

Buffer operation ...................................... 738

Bulk-in transfer ..................................... 1019

Bulk-out transfer ................................... 1018

Burst access mode................................... 414

Burst mode.............................................. 492

Burst ROM interface....................... 233, 265

Bus access modes.................................... 413

Bus arbitration......................................... 367

Bus configuration.................................... 220

Bus controller (BSC)............................... 183

Bus cycle division ................................... 576

Bus mode ................................................ 491

Bus release .............................................. 360

Bus width ................................................ 232

Bus-released state...................................... 76

Byte control SRAM interface ......... 233, 257

Cascaded connection............................... 836

Cascaded operation ................................. 742

Chain transfer.......................................... 583

Chip select signals................................... 230

Clock pulse generator ........................... 1221

Clock synchronization cycle (Tsy).......... 222

Clocked synchronous mode .................... 929

Cluster transfer dual address mode ......... 531

H8SX/1663R Datasheet(PDF) 1493 Page - Renesas Technology Corp

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