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H8SX/1663M Datasheet(PDF) 1011 Page - Renesas Technology Corp

Part # H8SX/1663M
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M Datasheet(HTML) 1011 Page - Renesas Technology Corp

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Section 20 USB Function Module (USB)
Rev. 2.00 Sep. 24, 2008 Page 979 of 1468
REJ09B0412-0200
20.3.11
EP0o Data Register (EPDR0o)
EPDR0o is an 8-byte receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive data
other than setup commands. When data is received successfully, EP0oTS in interrupt flag register
0 is set, and the number of receive bytes is indicated in the EP0o receive data size register. After
the data has been read, setting EP0oRDFN in the trigger register enables the next packet to be
received. This FIFO buffer can be initialized by means of BP0oCLR in the FCLR register.
Bit
Bit Name
Initial Value
R/W
7
D7
0
R
6
D6
0
R
5
D5
0
R
4
D4
0
R
3
D3
0
R
2
D2
0
R
1
D1
0
R
0
D0
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
All 0
R
Data register for control-out transfer
20.3.12
EP0s Data Register (EPDR0s)
EPDR0s is an 8-byte FIFO buffer specifically for receiving endpoint 0 setup commands. Only the
setup command to be processed by the application is received. When command data is received
successfully, the SETUPTS bit in interrupt flag register 0 is set.
As a latest setup command must be received in high priority, if data is left in this buffer, it will be
overwritten with new data. If reception of the next command is started while the current command
is being read, command reception has priority, the read by the application is forcibly stopped, and
the read data is invalid.
Bit
Bit Name
Initial Value
R/W
7
D7
0
R
6
D6
0
R
5
D5
0
R
4
D4
0
R
3
D3
0
R
2
D2
0
R
1
D1
0
R
0
D0
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
All 0
R
Data register for storing the setup command at the
control-out transfer



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