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H8SX/1663M Datasheet(PDF) 1328 Page - Renesas Technology Corp

Part # H8SX/1663M
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M Datasheet(HTML) 1328 Page - Renesas Technology Corp

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Section 29 List of Registers
Rev. 2.00 Sep. 24, 2008 Page 1296 of 1468
REJ09B0412-0200
Register Name
Abbreviation
Number
of Bits
Address
Module
Data
Width
Access
Cycles
(Read/Write)
Deep standby backup register 12
DPSBKR12
8
H'FFBFC
SYSTEM
8
2I
φ/3Iφ
Deep standby backup register 13
DPSBKR13
8
H'FFBFD
SYSTEM
8
2I
φ/3Iφ
Deep standby backup register 14
DPSBKR14
8
H'FFBFE
SYSTEM
8
2I
φ/3Iφ
Deep standby backup register 15
DPSBKR15
8
H'FFBFF
SYSTEM
8
2I
φ/3Iφ
DMA source address register_0
DSAR_0
32
H'FFC00
DMAC_0
16
2I
φ/2Iφ
DMA destination address register_0
DDAR_0
32
H'FFC04
DMAC_0
16
2I
φ/2Iφ
DMA offset register_0
DOFR_0
32
H'FFC08
DMAC_0
16
2I
φ/2Iφ
DMA transfer count register_0
DTCR_0
32
H'FFC0C
DMAC_0
16
2I
φ/2Iφ
DMA block size register_0
DBSR_0
32
H'FFC10
DMAC_0
16
2I
φ/2Iφ
DMA mode control register_0
DMDR_0
32
H'FFC14
DMAC_0
16
2I
φ/2Iφ
DMA address control register_0
DACR_0
32
H'FFC18
DMAC_0
16
2I
φ/2Iφ
DMA source address register_1
DSAR_1
32
H'FFC20
DMAC_1
16
2I
φ/2Iφ
DMA destination address register_1
DDAR_1
32
H'FFC24
DMAC_1
16
2I
φ/2Iφ
DMA offset register_1
DOFR_1
32
H'FFC28
DMAC_1
16
2I
φ/2Iφ
DMA transfer count register_1
DTCR_1
32
H'FFC2C
DMAC_1
16
2I
φ/2Iφ
DMA block size register_1
DBSR_1
32
H'FFC30
DMAC_1
16
2I
φ/2Iφ
DMA mode control register_1
DMDR_1
32
H'FFC34
DMAC_1
16
2I
φ/2Iφ
DMA address control register_1
DACR_1
32
H'FFC38
DMAC_1
16
2I
φ/2Iφ
DMA source address register_2
DSAR_2
32
H'FFC40
DMAC_2
16
2I
φ/2Iφ
DMA destination address register_2
DDAR_2
32
H'FFC44
DMAC_2
16
2I
φ/2Iφ
DMA offset register_2
DOFR_2
32
H'FFC48
DMAC_2
16
2I
φ/2Iφ
DMA transfer count register_2
DTCR_2
32
H'FFC4C
DMAC_2
16
2I
φ/2Iφ
DMA block size register_2
DBSR_2
32
H'FFC50
DMAC_2
16
2I
φ/2Iφ
DMA mode control register_2
DMDR_2
32
H'FFC54
DMAC_2
16
2I
φ/2Iφ
DMA address control register_2
DACR_2
32
H'FFC58
DMAC_2
16
2I
φ/2Iφ
DMA source address register_3
DSAR_3
32
H'FFC60
DMAC_3
16
2I
φ/2Iφ
DMA destination address register_3
DDAR_3
32
H'FFC64
DMAC_3
16
2I
φ/2Iφ
DMA offset register_3
DOFR_3
32
H'FFC68
DMAC_3
16
2I
φ/2Iφ
DMA transfer count register_3
DTCR_3
32
H'FFC6C
DMAC_3
16
2I
φ/2Iφ
DMA block size register_3
DBSR_3
32
H'FFC70
DMAC_3
16
2I
φ/2Iφ
DMA mode control register_3
DMDR_3
32
H'FFC74
DMAC_3
16
2I
φ/2Iφ



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