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H8SX/1663M Datasheet(PDF) 1329 Page - Renesas Technology Corp

Part # H8SX/1663M
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M Datasheet(HTML) 1329 Page - Renesas Technology Corp

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Section 29 List of Registers
Rev. 2.00 Sep. 24, 2008 Page 1297 of 1468
REJ09B0412-0200
Register Name
Abbreviation
Number
of Bits
Address
Module
Data
Width
Access
Cycles
(Read/Write)
DMA address control register_3
DACR_3
32
H'FFC78
DMAC_3
16
2I
φ/2Iφ
EXDMA source address register_0
EDSAR_0
32
H'FFC80
EXDMAC_0
16
2I
φ/2Iφ
EXDMA destination address register_0
EDDAR_0
32
H'FFC84
EXDMAC_0
16
2I
φ/2Iφ
EXDMA offset register_0
EDOFR_0
32
H'FFC88
EXDMAC_0
16
2I
φ/2Iφ
EXDMA transfer count register_0
EDTCR_0
32
H'FFC8C
EXDMAC_0
16
2I
φ/2Iφ
EXDMA block size register_0
EDBSR_0
32
H'FFC90
EXDMAC_0
16
2I
φ/2Iφ
EXDMA mode control regisrer_0
EDMDR_0
32
H'FFC94
EXDMAC_0
16
2I
φ/2Iφ
EXDMA address control register_0
EDACR_0
32
H'FFC98
EXDMAC_0
16
2I
φ/2Iφ
EXDMA source address register_1
EDSAR_1
32
H'FFCA0
EXDMAC_1
16
2I
φ/2Iφ
EXDMA destination address register_1
EDDAR_1
32
H'FFCA4
EXDMAC_1
16
2I
φ/2Iφ
EXDMA offset register_1
EDOFR_1
32
H'FFCA8
EXDMAC_1
16
2I
φ/2Iφ
EXDMA transfer count register_1
EDTCR_1
32
H'FFCAC
EXDMAC_1
16
2I
φ/2Iφ
EXDMA block size register_1
EDBSR_1
32
H'FFCB0
EXDMAC_1
16
2I
φ/2Iφ
EXDMA mode control register_1
EDMDR_1
32
H'FFCB4
EXDMAC_1
16
2I
φ/2Iφ
EXDMA address control register_1
EDACR_1
32
H'FFCB8
EXDMAC_1
16
2I
φ/2Iφ
EXDMA source address register_2
EDSAR_2
32
H'FFCC0
EXDMAC_2
16
2I
φ/2Iφ
EXDMA destination address register_2
EDDAR_2
32
H'FFCC4
EXDMAC_2
16
2I
φ/2Iφ
EXDMA offset register_2
EDOFR_2
32
H'FFCC8
EXDMAC_2
16
2I
φ/2Iφ
EXDMA transfer count register_2
EDTCR_2
32
H'FFCCC
EXDMAC_2
16
2I
φ/2Iφ
EXDMA block size register_2
EDBSR_2
32
H'FFCD0
EXDMAC_2
16
2I
φ/2Iφ
EXDMA mode control register_2
EDMDR_2
32
H'FFCD4
EXDMAC_2
16
2I
φ/2Iφ
EXDMA address control register_2
EDACR_2
32
H'FFCD8
EXDMAC_2
16
2I
φ/2Iφ
EXDMA source address register_3
EDSAR_3
32
H'FFCE0
EXDMAC_3
16
2I
φ/2Iφ
EXDMA destination address register_3
EDDAR_3
32
H'FFCE4
EXDMAC_3
16
2I
φ/2Iφ
EXDMA offset register_3
EDOFR_3
32
H'FFCE8
EXDMAC_3
16
2I
φ/2Iφ
EXDMA transfer count register_3
EDTCR_3
32
H'FFCEC
EXDMAC_3
16
2I
φ/2Iφ
EXDMA block size register_3
EDBSR_3
32
H'FFCF0
EXDMAC_3
16
2I
φ/2Iφ
EXDMA mode control register_3
EDMDR_3
32
H'FFCF4
EXDMAC_3
16
2I
φ/2Iφ
EXDMA address control register_3
EDACR_3
32
H'FFCF8
EXDMAC_3
16
2I
φ/2Iφ
Cluster buffer register 0
CLSBR0
32
H'FFD00
EXDMAC
16
2I
φ/2Iφ
Cluster buffer register 1
CLSBR1
32
H'FFD04
EXDMAC
16
2I
φ/2Iφ



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